The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to a method of depositing an insulating layer on a semiconductor substrate using a high density plasma reactor which reduces the damage to the substrate caused by plasma charging.
Advanced MOS devices require multiple levels of metal interconnections and reduced feature sizes of less than 0.5 micron. These requirements place severe demands on the intermetal dielectric insulating films. Such insulating films must have good film integrity, must demonstrate good gap fill capability for structures with gaps less than 0.4 micron wide, and must be deposited at rates sufficient to maintain adequate throughput. Recent developmental efforts have found that SiO.sub.2 films deposited by high density plasma chemical vapor deposition (CVD) processes meet these film requirements.
One known high density plasma CVD process is conducted in an electron cyclotron resonance (ECR) reactor. FIG. 1 shows a typical ECR system 100 known in the art. A substrate 106 rests on a chuck 104 disposed inside a plasma chamber 116. Chuck 104 may be either an electrostatic chuck (ESC) or a mechanical chuck and may be biased by a RF generator 102. A turbomolecular pump 110 controls the flow of hydrogen inside plasma chamber 116. A wave guide 112 brings microwaves inside source chamber 114, which is located above plasma chamber 116. Large magnets 108 surrounding source chamber 114 generate a magnetic field that sets up a resonance zone inside the source chamber, where the electrons gyrate at the same frequency as the microwave. As a result, a plasma is generated below the source and spreads out following the magnetic field lines representatively shown as lines 120 and 122 inside plasma chamber 116 and onto substrate 106. Outer magnet 124 and inner magnet 126 are used to fine focus this plasma.
In the formation of an SiO.sub.2 film, oxygen and argon gases are fed into source chamber 114. An ion beam of argon and oxygen is extracted from source chamber 114 and is directed toward substrate 106. Silane (SiH.sub.4) is fed into plasma chamber 116 through manifold 118 as shown in FIG. 1. The silane is absorbed onto the surface of substrate 106 and reacts with oxygen ions to form the SiO.sub.2 film.
A conventional gap fill recipe for filling gaps less than 0.4 micron wide in structures with an aspect ratio greater than 2 (the aspect ratio of a space to be filled being defined by the height of the space divided by the width of the space) calls for the application of sufficient RF power, generally about 1450 W to about 1750 W for an 8 inch wafer at normal gas flow rates, to obtain an etch to deposition (E/D) ratio of about 32%. The B/D ratio is defined as the deposition rate reduction due to RF sputter etching divided by the deposition rate without sputter etching. Thus, a higher E/D ratio provides better gap fill capability but at the cost of lower deposition rate. The application of RF power causes sputter etching by the argon ion beam to occur on the surface of the substrate. This argon sputter etch preferentially occurs at a 45.degree. angle which leads to faceting at the corners of exposed surfaces. As a result, the deposited film does not neck off or "breadloaf" at the tops of metal lines and cause voids to be formed in the film. The E/D ratio of 32% optimizes the gap fill capability of the deposited film while satisfying the need to maintain adequate throughput.
The continuing trend in advanced MOS devices is toward the use of extremely thin gate oxides having a thickness of about 40 angstroms. Unfortunately, the conventional gap fill recipe using an E/D ratio of 32% cannot be used in the fabrication of such IC's because damage to thin gate oxides may occur during deposition of the gap fill layer. This damage may result from the high ion current, J.sub.i, of high density plasma. If the plasma is not uniform across the substrate, then a current imbalance occurs in the substrate. The application of RF power, which itself is somewhat intrinsically nonuniform, causes a voltage to build up in the substrate. This voltage allows the current from the plasma to flow in the substrate to the gate oxides of underlying MOS transistors. Unfortunately, when the amount of current exceeds the capacity of the gate oxide, damage to the gate oxides may occur leading to gate leakage or oxide breakdown.
In an attempt to prevent such charging damage to gate oxides from occurring during high density plasma CVD processing, it has been proposed to first deposit an oxide protection layer without the application of RF power, i.e., a zero bias protection layer. Such a protection layer, however, is nonconformal in that it tends to "breadloaf" at the tops of metal lines. Referring to FIG. 2, substrate 200 includes structures 202 defining trenches 204 therebetween. Zero bias protection layer 206 builds up at the top corners of structures 202 and necks off trenches 204 which results in the formation of voids 208. Unfortunately, this effect may become even more pronounced when filling gaps having dimensions that are less than about 0.4 micron wide with an aspect ratio greater than 2. Furthermore, sidewall coverage is very thin and the dielectric integrity of the layer is relatively low. Consequently, a zero bias protection layer is not acceptable for use in filling gaps less than about 0.4 micron wide.
In view of the above, what is needed are methods and apparatuses for depositing a high quality (i.e., high dielectric integrity) insulating layer to fill gaps between high aspect ratio structures (i.e., structures having an aspect ratio greater than 2) using a high density plasma CVD process which prevents or reduces damaging side effects to the underlying substrate caused by plasma charging.